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Altera_Forum's avatar
Altera_Forum
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10 years ago

Timing Optimized VHDL Code

I'm looking for coding guidelines, rules, online resources, examples, etc. on how to write VHDL code that helps me achieve a higher fmax for my FPGA design. Does anybody have any good recommend...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

I'm gonna bump up that thread one more time.

What I had in mind were things like to use certain state machine encodings.

I also think I remember reading that counters with many bits make it difficult to reach higher frequencies.

Those are just two examples I came across, not sure if those are really significant.

Is there any good literature about that topic?