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DeusMMJr's avatar
DeusMMJr
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7 years ago

Timing issues using Arria 10 Dev kit for massive design

Hi, i'm working with a huge design using Arria 10 Dev kit and i'm facing with timing issues after signoff analysis. These time issues are associated specially with DSP blocks where long combinational...
GuaBin_N_Intel's avatar
GuaBin_N_Intel
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7 years ago

Yes, you have to reduce the comb path if the logic level is too many. Have you registered the output of DSP block? It would help if you could pipeline those outputs to traverse much longer distance in the path( more LABs).