Timing fails for reset line

You haven't indicated if your reset signals are pre-synchronised to each clock domain.

If not, you need a two stage synchroniser for each domain reset. These two registers themselves be set as false paths. You may then apply the reset to the asynchronous ports of flips (and check recovery/removal) or apply it synchronously to flips(and check ordinary tSU/tH). notice also that

clock speed has little effect on hold/removal violations which may occur at any speed unlike tSU/recovery violations which are the limiting factor for fmax