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1) how to best to choose global constraints like Tsu, Th and Tco
2) how to deal with small sections of problem logic that doesn't meet global timing
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1) You need to choose your I/O timing constraints based on the tco/min tco of the devices driving the FPGA, the tsu/th of the devices driven by the FPGA, clock skew on the board, and data delay on the board. (If you don't know the board delay numbers, then make your constraints a little tighter than they would be calculated from just the external device I/O timing.) I haven't looked at this in the Quartus handbook in a while and don't remember how much how-to detail is there, but I found some basic information with just a quick check. In the Volume 3, Section II mentioned in the other post, I found calculations of input and output delays (correspond to tsu and tco) using the board and external-device information in Chapter 8. This is the Classic Timing Analyzer chapter, but the calculation is the same for TimeQuest (Chapter 6 for TimeQuest might have the same thing). Chapter 7 has some information on how the input/output delay forms of these timing constraints correspond to the tsu/th/tco/min tco forms of the constraints.
2) If your timing constraints are correct (including any applicable timing exceptions like multicycles and false paths), then how to deal with timing violations is an issue separate from timing constraints, choice of timing analyzer, etc. The solution to your problem can range from simple to very complex. There is probably no document that tells everything on this subject, but there is some material in the Quartus Handbook in Volume 2, Section III, "Area, Timing and Power Optimization".
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