Timing Constraints Material

To answer more specific points: All of my IP meets timing. I would recommend that to be a good goal. [Although I'm not using NIOS] If your multiple timing domains are giving plentiful invalid errors, I would recommend first put more effort into clock bridges, and if you still need to switch to TimeQuest. By clock bridging I mean if you have a signal that goes from one clock domain to another and you have verified it is OK because the design tolerates the signal captured to the new clock domain on no particular clock edge, then sample the signal to the new clock domain, or edge detect (as a minimum). Then you will have a single register in the old domain going to a single register in the new domain, which will be easy to give a different timing assignment that works for you, ignore or min for example. If you can't relax timing requirements, that implies you need dual clock fifo's or the like.

If this isn't clear, shoot me an email and I'll find the right chapter in a VHDL/verilog book for some good reading about clock domains... The Quartus handbook has enough reading to cure a month's worth of insomnia.:)