Timing constraints for virtual pins

If your <insertcolorhere> Outputs feed other logic, you do not need to constrain them at all. From what I can gather you're trying to cut down on compile times and singling out that partition into a standalone project?

Well, since register to register usually needs no constraining if in same clock domain, simply put a DFF synchronous to your Clk signal in between virtual pins and your core. Quartus will then try to meet timing to and from those DFFs and you can check their states in Signaltap or Simulator. That will represent your design better, than using virtual pins directly.

On another note, I don't think one needs to constrain virtual pins at all, since they're just a placeholder. Without a specific physical place, Q2 cannot give you correct timings anyway.

What CLK speeds are we talking anyways?