Timing Constraints for Source Sync Interface with clock coming out of FSM (not PLL)

Thanks, I didn't find that because I didn't really know what I had to look for.

So what I take from that example is:

1) I have my FSM clock:

create_clock -period 20.0 -name clk_in [get_ports {clk_in}]

For outputs:

2) I have the output clock that I drive out of the FSM

create_generated_clock -invert divide_by 2 -name SCLK -source [get_ports clk_in] [get_ports SCLK]

-> divided by 2 because the frequency is divided by 2 in the FSM

-> inverted because I drive signals at the rising edge of clk_in, but the slave samples at the falling edge of SCLK

3) Set output delays

set_output_delay -clock SCLK -max 5 [get_ports {MOSI}] # setup time of slave, MOSI is FPGA output

set_output_delay -clock SCLK -min -5 [get_ports {MOSI}] # hold time of slave, MOSI is FPGA output

For inputs:

4) the same derived clock as above

-> because the slave drives signals at the rising edge of SCLK, but I sample at the falling edge of SCLK

5) Set input delays

set_input_delay -clock SCLK -max 15 [get_ports {MISO}] # Tco of external device, MISO is FPGA input

set_input_delay -clock SCLK -min 15 [get_ports {MISO}] # min Tco of external device, MISO is FPGA input