timing constraint

I have to ask why you want the path delays to be the same. As long as the signal is at each register, with sufficient setup time before the relevant clock edge, the register will acquire the right value.

You can/should constrain your design to tell Quartus how this particular input signal behaves by setting any relevant input delay. Then Quatus will deal with the placement appropriately to ensure each register has the setup time require or it'll report a timing violation if it can't meet your constraint.

Have a read of Quartus' online help on timing constraints: specifying timing constraints and exceptions (http://quartushelp.altera.com/14.0/master.htm#mergedprojects/analyze/sta/sta_pro_constraints.htm?gsa_pos=1&wt.oss_r=1&wt.oss=adding timing constraints)

Regards,

Alex