timing constraint for clock mux and how to set output delay

I once saw a large clock mux get synthesized into some ugly logic. It wasn't a mux tree like you're showing here. Instead, it had a larger blob, and though I forget the exact details, but in one case the clock selected went through two different paths through the LUT blob. It was technically correct from the logic, but it did glitch. This was probably ten years ago, but I've been paranoid since then and always hand-code as 2:1 muxes feeding each other and put KEEPS on each stage. Note that Settings -> Analysis & Synthesis -> More Settings has an option called Clock Mux Protection and has the following description:

Causes the multiplexers in the clock network to be decomposed to 2to1 multiplexer trees, and protected from being merged with, or transferred to, other logic. This option helps the TimeQuest timing analyzer to understand clock behavior.

So I think synthesis is going to try and do this naturally and I'm being paranoid. I don't know if there are any reports when this occurs, although your Technology Map Viewer looks correct.