timing constraint for clock mux and how to set output delay

Ryan,

Thanks for the explanation. You recommended to use 2to1 mux to create 8 to 1 mux with "synthesis keep" on wires. you said "This is to avoid toggling from unselected clocks causing your output to glitch. ". Can you please explain the reason behind that? I did not follow that because I did not want to rewrite all clock constraints at that time. My clock output is toggling even when no input clock was selected. I put data and clock together in the mux ( I have 8 different channels of data and clock to be muxed). please see the technology map viewer shot for the clock mux portion in my design.