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Altera_Forum
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13 years ago

timing constraint for clock mux and how to set output delay

Hi all, I have to constrain the output pins of my design by using "set_output_delay." The reference clock for those outputs pins comes from a clock mux. I've check the following link to kno...
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Altera_Forum
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12 years ago

Hi Ryan,

Thanks for the reply. Yes it is already in the IO. I found out this morning when I search IOs in the property resource editor. The compiler issued a warning for some other reasons like you said in your reply. It is Stratix device and I use Megafunction to generate the DDIOs. I have attached the screen short of the property resource editor.

Thanks again.

https://www.alteraforum.com/forum/attachment.php?attachmentid=9537