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Altera_Forum
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12 years ago

timing constraint for clock mux and how to set output delay

Hi all, I have to constrain the output pins of my design by using "set_output_delay." The reference clock for those outputs pins comes from a clock mux. I've check the following link to kno...
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Altera_Forum
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11 years ago

Hi Ryan,

Thanks for the reply. Yes you are right. It is just a warning but it already in the IO. Compiler just issued those warning for some other reason like you said in your reply. This morning, I found out when I tried to located the outputs and inputs in the chip planner and resource property editor and found those are already packed in the IOs. It is a Stratix device. I use the Megafunction to generate ddio. Attached are some screen shots in resource property editor. Thanks again.

http://www.alteraforum.com/forum/attachment.php?attachmentid=9536&stc=1