Forum Discussion
Altera_Forum
Honored Contributor
13 years agotiming constraint for clock mux and how to set output delay
Hi all, I have to constrain the output pins of my design by using "set_output_delay." The reference clock for those outputs pins comes from a clock mux. I've check the following link to kno...
Altera_Forum
Honored Contributor
12 years agoWhat device? You used the altddio megafunction? Assuming the device has DDIO and you used the megafunction, the fitter has to use the DDIO cell because it can't put it in logic. How are you sure it's not using the I/O cell, i.e. is it a warning you're getting or are you looking to make sure it's not there? Perhaps it is using it because it has to, and then ignores the assignment because there's not a single-register it can push in, or something silly like that.
I used to use Fast Input/Output assignments all the time, but haven't used them in years. I find the fitter does a good job packing them automatically, and if you have I/O timing assignments(which you should for anything you care about), it should always put them in the I/O cell if that's what's necessary to close timing.