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Altera_Forum's avatar
Altera_Forum
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12 years ago

timing constraint for clock mux and how to set output delay

Hi all, I have to constrain the output pins of my design by using "set_output_delay." The reference clock for those outputs pins comes from a clock mux. I've check the following link to kno...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Hi Ryan,

Thanks for the quick reply. I got it corrected now ( getting the targets for the clocks, mux outputs).

I have one more question. I created DDIO for data and clock to create synchronous clock interface (SDR). But fitter ignores the fast output register "on" settings. Any idea where should I look at it?