timing constraint for clock mux and how to set output delay

How come you're applying the generated clock to the LUT inputs(dataa, datab, etc.) instead of the LUT output. When doing a mux, I would recommend something like:

create_generated_clock -name A_muxed0~0_dnclk[0] -source [get_ports {dnclk[0]}] [get_pins {umuxa|Mux0~0|combout}]

create_generated_clock -name A_muxed0~0_dnclk[1] -source [get_ports {dnclk[1]}] [get_pins {umuxa|Mux0~0|combout}] -add

This way it doesn't matter which pin dnclk[1:0] comes in on.

Note that for an 8:1 mux, it is recommended to build that out of 2:1 muxes and put keeps on them, e.g. something like:

(* keep *) wire muxa,muxb, muxc,muxd,muxe,muxf,muxg;

assign muxa = s[0] ? a:b;

assign muxb =s[0] ? c:d;

assign muxc = s[0] ? e:f;

assign muxd = s[0] ? g:h;

assign muxe = s[1] ? muxa : muxb;

assign muxf = s[1] ? muxc : muxd;

assign muxg = s[2] ? muxe : muxf;

I did that quick, but something like that. This is to avoid toggling from unselected clocks causing your output to glitch.