timing constraint for clock mux and how to set output delay

Ryan,

I am using:

get_pins {umaxa|Mux0~0|datab}

in my create_generated_clock to constrain clock mux (8 to 1 mux). If I change some areas of the source code (not related to the mux) and recompiled, I found out those clocks coming into the mux dataa, datab, datac, datad pins are changed and my SDC statements are not valid anymore. Is there any way to call out get_pins which tolerant the mux input pin changes because of the Quartus compiler?

Thanks,

my sdc:# #mux0~0

create_generated_clock -name A_muxed0~0_dnclk[0] -source [get_ports {dnclk[0]}] [get_pins {umuxa|Mux0~0|datad}]

create_generated_clock -name A_muxed0~0_dnclk[1] -source [get_ports {dnclk[1]}] [get_pins {umuxa|Mux0~0|datac}] -add# #mux0~1

create_generated_clock -name A_muxed0~1_dnclk[2] -source [get_ports {dnclk[2]}] [get_pins {umuxa|Mux0~1|datac}]

create_generated_clock -name A_muxed0~1_dnclk[3] -source [get_ports {dnclk[3]}] [get_pins {umuxa|Mux0~1|datab}] -add

create_generated_clock -name A_muxed0~1_dnclk[0] -source [get_pins {umuxa|Mux0~0|datad}] -master_clock A_muxed0~0_dnclk[0] [get_pins {umuxa|Mux0~1|dataa}] -add

create_generated_clock -name A_muxed0~1_dnclk[1] -source [get_pins {umuxa|Mux0~0|datac}] -master_clock A_muxed0~0_dnclk[1] [get_pins {umuxa|Mux0~1|dataa}] -add