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Altera_Forum
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10 years ago

Timing constrain between pll clock and clock divisor

Hi, i have a PLL that generate three clock frequencies: 10MHz, 20MHz and 48MHz. The 20MHz clock is used to generate a 555KHz clock dividing the 20Mhz by 36. I setted up the Timing analyzer with...
Altera_Forum's avatar
Altera_Forum
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10 years ago

Another question:

What about the PLL input clock?

I must insert also the PLL input clock in the second group? (PLL input clock is 20MHz from an external oscillator)