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Altera_Forum
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11 years ago

Timing constrain between pll clock and clock divisor

Hi, i have a PLL that generate three clock frequencies: 10MHz, 20MHz and 48MHz. The 20MHz clock is used to generate a 555KHz clock dividing the 20Mhz by 36. I setted up the Timing analyzer with...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

derive_pll_clocks

Then launch TimeQuest and run "Report Clocks". This will give the exact clock names for each one, and copy them to add a constraint like so:

set_clock_groups -asynchronous

-group {48mhz_clk}

-group {10mhz_clk

20mhz_clk

555khz_clk}

Naturally, your design needs to be able to handle any paths between 48MHz and the other domains as being asynchronous.