Timing Analyzer: Clock Skew problem

Question

Dear all,   I am doing a project in which I need to use the audio codec of my DE2-35 development kit. I have used the i2sound demo provided in DE2 manual and modified it to take sound input (serial input from ADC) convert it to parallel and again parallel to serial for DAC (codec) then to the speaker.   However when i added some processing blocks in between the serial to parallel and parallel to serial blocks the timing analyzer showed the following errors.... :(    
Info: Found hold time violation between source  pin or register "CLOCK_500:inst4|COUNTER_500" and destination pin or register "i2c:inst|SD_COUNTER" for clock "50MHZ" (Hold time is 1.21 ns)
 Info: + Largest clock skew is 2.529 ns
  Info: + Longest clock path from clock "50MHZ" to destination register is 5.219 ns
   Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = '50MHZ'
   Info: 2: + IC(0.780 ns) + CELL(0.787 ns) = 2.566 ns; Loc. = LCFF_X7_Y18_N21; Fanout = 6; REG Node = 'CLOCK_500:inst4|COUNTER_500'
   Info: 3: + IC(1.077 ns) + CELL(0.000 ns) = 3.643 ns; Loc. = CLKCTRL_G1; Fanout = 29; COMB Node = 'CLOCK_500:inst4|COUNTER_500~clkctrl'
   Info: 4: + IC(1.039 ns) + CELL(0.537 ns) = 5.219 ns; Loc. = LCFF_X8_Y18_N19; Fanout = 14; REG Node = 'i2c:inst|SD_COUNTER'
   Info: Total cell delay = 2.323 ns ( 44.51 % )
   Info: Total interconnect delay = 2.896 ns ( 55.49 % )
  Info: - Shortest clock path from clock "50MHZ" to source register is 2.690 ns
   Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = '50MHZ'
   Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 10; COMB Node = '50MHZ~clkctrl'
   Info: 3: + IC(1.036 ns) + CELL(0.537 ns) = 2.690 ns; Loc. = LCFF_X7_Y18_N23; Fanout = 2; REG Node = 'CLOCK_500:inst4|COUNTER_500'
   Info: Total cell delay = 1.536 ns ( 57.10 % )
   Info: Total interconnect delay = 1.154 ns ( 42.90 % )
 Info: - Micro clock to output delay of source is 0.250 ns
 Info: - Shortest register to register delay is 1.335 ns
  Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X7_Y18_N23; Fanout = 2; REG Node = 'CLOCK_500:inst4|COUNTER_500'
  Info: 2: + IC(0.310 ns) + CELL(0.150 ns) = 0.460 ns; Loc. = LCCOMB_X7_Y18_N30; Fanout = 6; COMB Node = 'CLOCK_500:inst4|GO~31'
  Info: 3: + IC(0.365 ns) + CELL(0.510 ns) = 1.335 ns; Loc. = LCFF_X8_Y18_N19; Fanout = 14; REG Node = 'i2c:inst|SD_COUNTER'
  Info: Total cell delay = 0.660 ns ( 49.44 % )
  Info: Total interconnect delay = 0.675 ns ( 50.56 % )
 Info: + Micro hold delay of destination is 0.266 ns
Info: Started Full Compilation at Tue May 04 17:18:25 2010 Central Asia Standard Time
Info: Ended Full Compilation at Tue May 04 17:18:28 2010 Central Asia Standard Time
Info: Started Full Compilation at Tue May 04 17:18:50 2010 Central Asia Standard Time
Info: Ended Full Compilation at Tue May 04 17:19:38 2010 Central Asia Standard Time
Info: Found hold time violation between source  pin or register "CLOCK_500:inst4|COUNTER_500" and destination pin or register "i2c:inst|SD_COUNTER" for clock "50MHZ" (Hold time is 1.21 ns)
 Info: + Largest clock skew is 2.529 ns
  Info: + Longest clock path from clock "50MHZ" to destination register is 5.219 ns
   Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = '50MHZ'
   Info: 2: + IC(0.780 ns) + CELL(0.787 ns) = 2.566 ns; Loc. = LCFF_X7_Y18_N21; Fanout = 6; REG Node = 'CLOCK_500:inst4|COUNTER_500'
   Info: 3: + IC(1.077 ns) + CELL(0.000 ns) = 3.643 ns; Loc. = CLKCTRL_G1; Fanout = 29; COMB Node = 'CLOCK_500:inst4|COUNTER_500~clkctrl'
   Info: 4: + IC(1.039 ns) + CELL(0.537 ns) = 5.219 ns; Loc. = LCFF_X8_Y18_N19; Fanout = 14; REG Node = 'i2c:inst|SD_COUNTER'
   Info: Total cell delay = 2.323 ns ( 44.51 % )
   Info: Total interconnect delay = 2.896 ns ( 55.49 % )
  Info: - Shortest clock path from clock "50MHZ" to source register is 2.690 ns
   Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = '50MHZ'
   Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 10; COMB Node = '50MHZ~clkctrl'
   Info: 3: + IC(1.036 ns) + CELL(0.537 ns) = 2.690 ns; Loc. = LCFF_X7_Y18_N23; Fanout = 2; REG Node = 'CLOCK_500:inst4|COUNTER_500'
   Info: Total cell delay = 1.536 ns ( 57.10 % )
   Info: Total interconnect delay = 1.154 ns ( 42.90 % )
 Info: - Micro clock to output delay of source is 0.250 ns
 Info: - Shortest register to register delay is 1.335 ns
  Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X7_Y18_N23; Fanout = 2; REG Node = 'CLOCK_500:inst4|COUNTER_500'
  Info: 2: + IC(0.310 ns) + CELL(0.150 ns) = 0.460 ns; Loc. = LCCOMB_X7_Y18_N30; Fanout = 6; COMB Node = 'CLOCK_500:inst4|GO~31'
  Info: 3: + IC(0.365 ns) + CELL(0.510 ns) = 1.335 ns; Loc. = LCFF_X8_Y18_N19; Fanout = 14; REG Node = 'i2c:inst|SD_COUNTER'
  Info: Total cell delay = 0.660 ns ( 49.44 % )
  Info: Total interconnect delay = 0.675 ns ( 50.56 % )
 Info: + Micro hold delay of destination is 0.266 ns
   can somebody explain me what is wrong and suggest me any solution!    With regards omeecd

altera_forum · Answer

--- Quote Start ---  Dear all,   I am doing a project in which I need to use the audio codec of my DE2-35 development kit. I have used the i2sound demo provided in DE2 manual and modified it to take sound input (serial input from ADC) convert it to parallel and again parallel to serial for DAC (codec) then to the speaker.   However when i added some processing blocks in between the serial to parallel and parallel to serial blocks the timing analyzer showed the following errors.... :(    
Info: Found hold time violation between source  pin or register "CLOCK_500:inst4|COUNTER_500" and destination pin or register "i2c:inst|SD_COUNTER" for clock "50MHZ" (Hold time is 1.21 ns)
 Info: + Largest clock skew is 2.529 ns
  Info: + Longest clock path from clock "50MHZ" to destination register is 5.219 ns
   Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = '50MHZ'
   Info: 2: + IC(0.780 ns) + CELL(0.787 ns) = 2.566 ns; Loc. = LCFF_X7_Y18_N21; Fanout = 6; REG Node = 'CLOCK_500:inst4|COUNTER_500'
   Info: 3: + IC(1.077 ns) + CELL(0.000 ns) = 3.643 ns; Loc. = CLKCTRL_G1; Fanout = 29; COMB Node = 'CLOCK_500:inst4|COUNTER_500~clkctrl'
   Info: 4: + IC(1.039 ns) + CELL(0.537 ns) = 5.219 ns; Loc. = LCFF_X8_Y18_N19; Fanout = 14; REG Node = 'i2c:inst|SD_COUNTER'
   Info: Total cell delay = 2.323 ns ( 44.51 % )
   Info: Total interconnect delay = 2.896 ns ( 55.49 % )
  Info: - Shortest clock path from clock "50MHZ" to source register is 2.690 ns
   Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = '50MHZ'
   Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 10; COMB Node = '50MHZ~clkctrl'
   Info: 3: + IC(1.036 ns) + CELL(0.537 ns) = 2.690 ns; Loc. = LCFF_X7_Y18_N23; Fanout = 2; REG Node = 'CLOCK_500:inst4|COUNTER_500'
   Info: Total cell delay = 1.536 ns ( 57.10 % )
   Info: Total interconnect delay = 1.154 ns ( 42.90 % )
 Info: - Micro clock to output delay of source is 0.250 ns
 Info: - Shortest register to register delay is 1.335 ns
  Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X7_Y18_N23; Fanout = 2; REG Node = 'CLOCK_500:inst4|COUNTER_500'
  Info: 2: + IC(0.310 ns) + CELL(0.150 ns) = 0.460 ns; Loc. = LCCOMB_X7_Y18_N30; Fanout = 6; COMB Node = 'CLOCK_500:inst4|GO~31'
  Info: 3: + IC(0.365 ns) + CELL(0.510 ns) = 1.335 ns; Loc. = LCFF_X8_Y18_N19; Fanout = 14; REG Node = 'i2c:inst|SD_COUNTER'
  Info: Total cell delay = 0.660 ns ( 49.44 % )
  Info: Total interconnect delay = 0.675 ns ( 50.56 % )
 Info: + Micro hold delay of destination is 0.266 ns
Info: Started Full Compilation at Tue May 04 17:18:25 2010 Central Asia Standard Time
Info: Ended Full Compilation at Tue May 04 17:18:28 2010 Central Asia Standard Time
Info: Started Full Compilation at Tue May 04 17:18:50 2010 Central Asia Standard Time
Info: Ended Full Compilation at Tue May 04 17:19:38 2010 Central Asia Standard Time
Info: Found hold time violation between source  pin or register "CLOCK_500:inst4|COUNTER_500" and destination pin or register "i2c:inst|SD_COUNTER" for clock "50MHZ" (Hold time is 1.21 ns)
 Info: + Largest clock skew is 2.529 ns
  Info: + Longest clock path from clock "50MHZ" to destination register is 5.219 ns
   Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = '50MHZ'
   Info: 2: + IC(0.780 ns) + CELL(0.787 ns) = 2.566 ns; Loc. = LCFF_X7_Y18_N21; Fanout = 6; REG Node = 'CLOCK_500:inst4|COUNTER_500'
   Info: 3: + IC(1.077 ns) + CELL(0.000 ns) = 3.643 ns; Loc. = CLKCTRL_G1; Fanout = 29; COMB Node = 'CLOCK_500:inst4|COUNTER_500~clkctrl'
   Info: 4: + IC(1.039 ns) + CELL(0.537 ns) = 5.219 ns; Loc. = LCFF_X8_Y18_N19; Fanout = 14; REG Node = 'i2c:inst|SD_COUNTER'
   Info: Total cell delay = 2.323 ns ( 44.51 % )
   Info: Total interconnect delay = 2.896 ns ( 55.49 % )
  Info: - Shortest clock path from clock "50MHZ" to source register is 2.690 ns
   Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = '50MHZ'
   Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 10; COMB Node = '50MHZ~clkctrl'
   Info: 3: + IC(1.036 ns) + CELL(0.537 ns) = 2.690 ns; Loc. = LCFF_X7_Y18_N23; Fanout = 2; REG Node = 'CLOCK_500:inst4|COUNTER_500'
   Info: Total cell delay = 1.536 ns ( 57.10 % )
   Info: Total interconnect delay = 1.154 ns ( 42.90 % )
 Info: - Micro clock to output delay of source is 0.250 ns
 Info: - Shortest register to register delay is 1.335 ns
  Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X7_Y18_N23; Fanout = 2; REG Node = 'CLOCK_500:inst4|COUNTER_500'
  Info: 2: + IC(0.310 ns) + CELL(0.150 ns) = 0.460 ns; Loc. = LCCOMB_X7_Y18_N30; Fanout = 6; COMB Node = 'CLOCK_500:inst4|GO~31'
  Info: 3: + IC(0.365 ns) + CELL(0.510 ns) = 1.335 ns; Loc. = LCFF_X8_Y18_N19; Fanout = 14; REG Node = 'i2c:inst|SD_COUNTER'
  Info: Total cell delay = 0.660 ns ( 49.44 % )
  Info: Total interconnect delay = 0.675 ns ( 50.56 % )
 Info: + Micro hold delay of destination is 0.266 ns
   can somebody explain me what is wrong and suggest me any solution!    With regards omeecd  --- Quote End ---    Hi,  the source and destination registers are clocked by different clocks which have different delays. The data delay is shorter than the clock skew ( that is difference of the clock delays). The data change occurs before the rising edge of the clock of the destination register.   kind regards  GPK

altera_forum · Answer

Can't be determined exactly without seeing the code, but it seems like you have used unsuitable clock dividers (ripple clock). You should follow Altera suggestions for clock dividers in the Quartus Software Handbook.

altera_forum · Answer

Thank you for your quick reply.

The problem is, i have just used these codes from altera's examples with the educational board. So, i'm confused about how to correct them.

Here are the files with the skew problem (Clock_500 and SD_counter are in these files).

I'll be glad to have any suggestion!

With regards

Omee

altera_forum · Answer

Dear All,

Here are my project files. I used the de2sound example and modified it. I tried to convert serial input data (from the codec) into parallel and then again from parallel to serial and pass it through the codec to the speaker. I have also allowed only one channel to pass.

The project, after compilation, shows clock skew problem... however the sound from the speaker is heard from only one channel and very clearly (i was expecting some distortion). Can anyone tell me whether this project is working properly or not?

With regards.

Omeecd

altera_forum · Answer

hello Omeecd,

For my project, i need to implement a ADC in DE2-115 board using Audio Codec.

The audio signal is tobe digitalised using ADC and stored on on-chip memory. Can you let me know, it is possible .

Am new to FPGA, so is ther any chance you code will be usefull as an example.

thanks,

vrv

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Timing Analyzer: Clock Skew problem

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