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Altera_Forum
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8 years ago

Timing Analysis: express frequency uncertainty of external oscillator

An external oscillator is connected to my FPGA. Its signal is used as a clock. There is an uncertainty of the oscillator frequency. The minimum frequency is 20 MHz and the maximum frequency is 25 MHz...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

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For your design - assuming a traditional static design consisting of registers and logic - you 'simply' need to constrain it for your faster clock.

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Which design would not work with this simple solution, for example? And what could I do then? Is this beyond the scope of the timing analyzer?