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Altera_Forum
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8 years ago

Timing Analysis: express frequency uncertainty of external oscillator

An external oscillator is connected to my FPGA. Its signal is used as a clock. There is an uncertainty of the oscillator frequency. The minimum frequency is 20 MHz and the maximum frequency is 25 MHz...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

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That's not what the set_clock_uncertainty is for.

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I already suspected it.

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Providing it runs at 25MHz it'll run quite happily at 20MHz.

You may need to be careful if you use PLLs or other timing related IP.

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Thanks a lot!