Forum Discussion
germano
New Contributor
New ContributorTiming analysis - Timing requirements not met
Hello,
When compiling my project I get two critical warning errors :
1. Critical Warning (14997): The FPGA to HPS SDRAM PLL reference clock path is not timing analyzed and could be subject to ji...
sstrell
Super Contributor
Super ContributorYou're missing your I/O timing constraints, set_input_delay and set_output_delay. All synchronous I/O need constraints. Asynchronous paths should be set as false paths. Run an analysis in the timing analyzer to see exactly which paths are failing timing. I'd recommend starting here:
https://cdrdv2.intel.com/v1/dl/getContent/653046?explicitVersion=true
