Honored Contributor
Honored ContributorWhat you have is a source synchronous center-aligned output case. If the $clk_125_p90 is the clock out of the PLL, you need to create another generated clock (e.g. clk_125_p90_out) and assign it to the output port that drives the clock out of the FPGA. This is the clock you will use to constrain your outputs to. I would suggest using set_output_delay constraints as follows:
set_output_delay -max OMD -clock {clk_125_p90_out} -add_delay [get_ports {data_out*}] set_output_delay -min OmD -clock {clk_125_p90_out} -add_delay [get_ports {data_out*}] where OMD = external device's tSU + max board clock-data skew, OmD = external device's -tH + min board clock-data skew, and data_out* are the data output port names for the data that goes with the output clock. If this DDR, then you will also need to constrain to the falling edge of the clock. set_output_delay -max OMD -clock {clk_125_p90_out} -add_delay -clock_fall [get_ports {data_out*}] set_output_delay -min OmD -clock {clk_125_p90_out} -add_delay -clock_fall [get_ports {data_out*}] One last thing. If this is DDR, then you will be using same edge capture, so you will need to add some set_false_path statements: set_false_path -setup -rise_from [get_clocks {clk125}] -fall_to [get_clocks {clk_125_p90_out}] set_false_path -setup -fall_from [get_clocks {clk125} -rise_to [get_clocks {clk_125_p90_out} set_false_path -hold -rise_from [get_clocks {clk125}] -rise_to[get_clocks {clk_125_p90_out}] set_false_path -hold -fall_from [get_clocks {clk125}] -fall_to[get_clocks {clk_125_p90_out}]
