Timequest: toggle synchronizer constraints?

To throw in an ignorant question. Is there any use of timing analysis for this problem? I see two aspects of analysis in this case:

Relation between both clocks and "clock properties" of the input signal, particularly keeping minimum pulse width.

Toggle synchronizers are applied to unrelated signals. Shouldn't it be sufficient to declare the input as such? Just cut the path.

Input signal property is a more difficult problem. If the signal is sourced from combinational logic, you can't guarantee to keep minimum pulsewidth and I doubt that Time Quest can check it all all. For a register source, it will be kept by nature. In other words, timing analysis is either useless or superfluous.

But I'm curious to here a more profound analysis.

Frank