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I have not used clock groups but my understanding of how they work is that it would specify that ALL signals from clock A to clock B will be excluded. I am trying to take a conservative approach where signals are excluded only by specific constraints for each signal. Clock groups would automatically exclude all signals and thus accidental domain crossings would no longer fail timing. Is my understanding of clock groups correct?
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Yeah, that sounds about right.
I'm not sure that you can get TimeQuest to give you a warning about unconstrained paths between clock domains, but you can probably write a Tcl procedure to generate a warning.
Start by seeing if my idea works "manually", and then figure out how to do it using Tcl.
1. Synthesize your design with missing clock crossing logic
2. Start the TimeQuest GUI
3. Run the "Report clock transfers" report
Look at this report. Then go back and add a cut timing path, or create an asynchronous timing group, and you'll see the clock crossing paths reported as "false path".
Your custom clock report could be to loop over all entries in this report, and check that each entry matches whatever crossings you allow.
What you're essentially trying to do is to manually/explicitly cut the timing-paths between the clock domains at the logic level.
Personally I prefer cutting clock domains using clock groups, since I know that I have clock-domain crossing logic across the necessary paths (typically bridges, or dual-ported RAMs).
Cheers,
Dave
Honored Contributor
