Forum Discussion
IDeyn
Contributor
ContributorTimeQuest strange behavior - seems like a bug in PLL output clock visualization
Hi all! Recently faced such problem - in the test project there are two PLLs, with input from two base input clocks. One clock is 50 MHz with waveform { 0.000 10.000 } and on also 50 MHz with wavef...
Abe
Frequent Contributor
Frequent ContributorI guess, when you're shifting the clocks manually without using the PLLs phase shift feature, then you would have to generate the output clocks manually using the create_generated_clocks constraints. The derive_pll_clocks works well when the PLL is used for phase shifting the clocks. It generates the required clocks with respect to the PLL configuration settings.
