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Altera_Forum
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10 years ago

Timequest: Source synchronous timing isn't moving when I adjust PLL

I have a bit of a confusing timing issue. I have a source synchronous DDR LVDS output interface in which the data and clock are centre aligned. This all passes timing and I am happy with all the ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

If you use the "create_ generated_clock" command in your SDC, yes; You should modify your constraints in order to reflect phase shift.

If you have used the "derive_pll_clocks" in the SDC file, no; It is automatically translated into appropriate commands.