Timequest SDRAM input: unconstrained and working vs closed and broken

Hi Mazel,

My understanding of the need for the multicycle is that it's to capture the data on the following edge as the PLL shift on its own is not enough to have the input data ready at the register so it should be held for the next edge. Most of the SDR examples I've found on this forum include a multicycle like this and I've tried both with and without :)

The memory is a ISSI IS42S16160B (http://www.issiusa.com/pdf/42s83200b-16160b.pdf), and for the delay calculations, I've followed AN 433 using system-centric approach:

- output max delay: tsu = 2ns (input data setup time tDS)

- output min delay: tH = 1ns (input data hold time tDH)

- input max delay: 6.4ns (Access Time From CLK tAC2) which corresponds to a UI of 20ns - tSU

- input min delay: 2.7ns (Output Data Hold Time tOH2)

I haven't included trace delays in those, but I think they're going to be sub 0.1ns for this board. The -2.7ns phase shift was selected based on http://www.pldworld.com/_altera/html/_excalibur/nios-sdram-tuning/sdram_pll_tuning.pdf and ~-3ns seems to be fairly typical for SDR SDRAM controllers at 50MHz.

Thanks,

Jamie