Timequest SDRAM input: unconstrained and working vs closed and broken

Hi,

I don't understand why you use a multicyle path. Both clocks have the same frequency...

The way I see your problem is that your constraints may be too strong, or maybe have a small calculation mistake (maybe not, it's just an hypothesis). Then, although the timing report gives you a setup violation, the PAR have made all it could to meet the timing and your system works fine because of the strong requirement.

While giving a multicycle path requirement, the PAR do not try to optimise the data alignement between sys_cllk and sdram_clk (you give it 2 periods to meet setup). The timing report is fine but you got timing failure at runtime.

Can you post your input and output delay calculation, also with your SDRAM datasheet data for these delays ?

hope it helps.