--- Quote Start ---
Your register example is different/complementary from a lot of what I've done, i.e. I try to explain how to enter the constraint. You quickly give the constraint and spend a lot of time analyzing the post-fit results and trying to close timing. Very valuable and something I haven't spent a lot of time on. They're very distinct things, as I sometimes work with people who talk about not being able to meet timing although they have incorrect constraints and can't read them. Not until the constraints are done should anyone worry about timing.
--- Quote End ---
That is an interesting observation.
The main reason I started that way, was to show in the GUI waveforms where those numbers end up.
My designs are often FPGA-to-FPGA, and I want to know the maximum clock rate over those paths. Given that I have no information on the 'external device' timing, I put in some random constraints, and move to analysis.
--- Quote Start ---
For asynchronous RAMs, TQ doesn't have any easy way to connect all the output addresses to the data coming back(there is one that's a painful hack). That makes it a two step process of constraining one side first, then using that to constrain the other side.
--- Quote End ---
I can live with that. My main complaint with the available TimeQuest documentation, is that it does not explain that anywhere.
--- Quote Start ---
Note that synchronous RAMs are very nice, in that you use the clock being sent off chip as the clock for set_input_delay constraints on the data coming back, and the whole round-trip read is analyzed correctly.
--- Quote End ---
I see the DE2-70 and NEEK have SSRAM. I'll add examples for those interfaces.
Cheers,
Dave
Honored Contributor
