--- Quote Start ---
get_timing_paths -long_help
By the way, just typing help in TimeQuest gives a list of libraries, and you can then help on them. For example, this is in "help sta". Kind of interesting to poke around. (You can also do "quartus_sh --qhelp" in a shell for a GUI version).
--- Quote End ---
Cool, I'll have a look around.
--- Quote Start ---
I've never seen this asked for, and assume you're scripting up something cool. Wanna share what it is?
--- Quote End ---
It could just be that I'm doing something wrong too :)
I'm interested in just seeing the individual delay contributions, and seeing how things change. Some of the examples I was playing with;
1) A simple register design with an 8-bit register from input ports back to output ports. Most of the timing delays on the signals were all very similar except for one signal. The (min-max) clock-to-output delays for all the signals was about the same, its just that one had larger output register delays ... weird. I'll post the example synthesis script and timing analysis.
2) An Avalon-MM slave SRAM controller, with generics to set the SRAM timing parameters. I then want to analyze all the clock-to-output delays, and using those calculate the minimum write pulse, minimum read pulse, and minimum setup/hold times relative to all signals. I'll see if I can convert it into some format where I can use a waveform viewer ... perhaps a value-change-dump file? I recall the Icarus verilog guys use GtkViewer to look at waveforms ... I'll check that out (or perhaps I can just use Modelsim).
3) Using the Resource Property editor, the Chip Planner, etc. to view how placement affects the delays.
I'd also like to see how these timings relate to the post-P&R Modelsim simulation results too.
Just curious ... but I'll try to put anything useful into a document for you to add to your wiki page.
Cheers,
Dave
Honored Contributor
