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Hi
You could call it source synchronous.
Problem is: the "clock output" looks like just another data signal for the timing analysis.
there are five registers, all clocked by one clock with 50MHz. four of them just register data and directly feed a pin.
the last one has output feeding a pin and connected to the input through an inverter, i.e. cuts the clock in half.
on the outside, this looks like a data bus with data transfer on both flanks. but yes, source synchronous. inside the fpga i just have five signals.
what I didn't try is to specify a clock on that fifth signal... but how to specify a clock that is active on both flanks? just double the speed?
thanks and best regards,
emanuel
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Hi Emanuel,
have a look to this application note:
http://www.altera.com/literature/an/an433.pdf?gsa_pos=1&wt.oss_r=1&wt.oss=an433&gsa_pos=1&wt.oss_r=1&wt.oss=an433 Maybe it will answer your questions.
Kind regards
GPK
Honored Contributor
