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Altera_Forum's avatar
Altera_Forum
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14 years ago

TimeQuest Question

Hi, I am a newby using timequest and I have a question. In my project there is a master clock of 30 MHz and I have a filter working at a freqeuency = master clock / 4. Should I write a multicy...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Depends.

a) If your filter is running on a divided clock generated by a PLL, you can just add a "derive_ppl_clocks" command to the .sdc. You could also manually use a "create_generated_clock" constrain though.

b) If your filter is running on a 1/4 clock enable, the multicycle path is the correct aproach.

c) If your filter is running on a divided clock generated by logic. you need a "create_generated_clock" command. "b" would be a better option though.