Timequest question using gated clocks

As far as I can see, Quartus just sucks whenever you generate a clock from logic aka divided clock (which seems to be what you are doing from the picture). To close timing at even relatively modest speeds on the Arria V series, I had to switch over to using clock enables for everything.

This sucks if your design only has a couple of high speed transitions and most of the logic is working at a much slower speed since the maximum frequency clock spine has to be routed to everything and costs power. However, Quartus/TimeQuest always seems to wind up with a massive uncertainty that it can't deal with when it routes a divided clock through a clock buffer.

I suspect that you could tweak this by hand to force it to work, but I suspect it is a fool's errand. I have learned over many years that fighting a broken tool is generally more work than adjusting the design to live within the limitations of the tool.