Timequest question using gated clocks

Thanks for your quick answer ! Yes 'slow_clk' is asynchronous to clk16384, but in fact there are 3 registers on slow_clk and slow_dat paths to insure metastability is not propagated. So we can consider that the signals are synchronous to clk16384.

Your command 'report_timing' is very interesting. I also tried the command :

report_timing -setup -npaths 10 -detail full_path -from_clock clk16384 -to_clock clkcoef -panel_name "s: clk(clk16384) -> clk(clkcoef)"

(note that in my design the gated clock name is 'clkcoef' instead of 'sclk_b').

It seems that the timing is ok, but it is difficult to understand because the output signal is in fact a fir IP from Quartus, and some sources are encrypted, such as the 'shift_in:in_coef' block.