Forum Discussion
Altera_Forum
Honored Contributor
12 years agorun:
report_timing -setup -npaths 10 -detail full_path -to_clock sclk_b -panel_name "s: -> clk(sclk_b)" First, Data Required Clock Path trace all the way back to the same source as the Data Required? That's usually the biggest mistake, when there's something wrong with the generated_clock assignment. Also, is slow_clk asynchronous to clk16384? If so, that first register will go metastable now and then, and you don't pipeline it to allow that metastability to settle before using it as a clock, so that could be a problem. (Most of the time this will work, and the metastability will only occur every once in a while, so you're failure rate might help determine if that's an issue)