Forum Discussion
The clock pessimism that you see in the timing report is caused when scaling is applied to the clock path to account for different on-chip variations that are not accounted for the primitive block timing models. The scaling factor is applied to all cells and nets on the launch clock path, data path, and capture clock path. Imagine now that there is a portion at the root of the clock tree where the launch clock and capture clock are the same. There is no need to apply any scaling/pessimism to this portion of the clock tree to account for cross chip process effects because these effects cancel each other out in the path (which makes sense since they are the same cells and nets). Since the this extra pessimism is artificial, it is being removed. This removal is what you see in the line "clock pessimism.
The obvious question might be why is the pessimism put on the common portion of the path to start with. I guess it is easier for the timers to remove it after the fact. Maybe doing it this way simplifies the data structures and reduces memory consumption. This is just a guess as to why it is done this way...