Timequest...need expert

What's the clock rate?

Technically, if you don't know the board delays you can't do it right. (What if there were 20ns of board skew between clock and data?) Less technically, let's just assume they clock and data are the same delay for now. Unless something is really messed up, that's probably pretty accurate. The nice thing with that is that they cancel out.

With that, what you have is correct. Just say 2ns and 5ns. When you look at the timing report -setup, you will see that your setup relationship is the clock period. The data gets to the FPGA 5ns later, and basically that means the FPGA needs to get the data to the register in (clock_period - 5ns) It will also subtract the clock delay in the FPGA, which is correct.