Honored Contributor
Honored ContributorThanks for the answer....I'm new with timing constraint and I need a little help...:)
I need to interface an ULPI transceiver to my FPGA...the transceiver generates clocks and data for the fpga as in the attach...(clock out and data out) As you can see data follows the rising edge fo clock after min 2 ns and max 5 ns.... I suppose that this should be the input delay (min, max) to impose if we hadn't the delays for the links between transceiver and fpga...this delays are not neglectable and must be taken into account but how??? I could use an FPGA centric method (skew method) to avoid taking into account these delays...but I don't understand how to proceed in this direction...i.e. not knowing board delays means that I don't the relation between clock and data at FPGA input...therefore I don't know how to proceed... Any help will be welcome... THX in advance Carlo
