Honored Contributor
Honored ContributorI read your full document. The register in my case is part of my reset sync IP that is stamped out many times throughout the design. While the "(* dont_merge *)" directive seems attractive, it will cause pretty much all of my resets in the design not to be optimized - which would probably be overkill and would ignore registers that can safely be combined.
What I will do later is disable the merge in Assignment Editor for that register only and see what happens. I am kind of not too comfortable with Quartus making that false analysis, but would like to make sure that I don't actually have an issue that is mis-reported. Too bad this is a big project and can't safely be shared - I would otherwise send it to Altera Support to see what they think.
