Honored Contributor
Honored ContributorSorry for the delay. Thanks for the clock suggestion. I found that the data arrival path did not have an originating clock. There was also a warning in the console indicating this:
Info: The source clock for this clock assignment cannot be reached. Clock: clk_16 might not have valid arrival time. I believe this was because my generated_clock definitions were incorrect. I tried creating a series of two generated clocks: 5khz and clk_16 However, I realized this is incorrect because the generation of this clk_16 is really latched by the 20 Mhz clock edge with a 5khz clock enable (see my original picture). Therefore I think I only need one create_generated_clock cmd which generates the clk_16 from the 20Mhz. The 5khz is basically irrelavent. (Is this when multicycles can be used if needed?) So my only generated_clock is: create_generated_clock -name clk_16 -source [get_pins {pll|clk[4]}] -divide_by 4000 [get_registers {component_A|i_component_A|clk_16}] This removes the warning and shows the Data Required Path from the data all the way back through the pll to the input clock pin. This now makes sense. I attatched the timing result of the slowest path. Note I did rename everything so please ignore the names if they don't look quite right. Thanks again.
