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Altera_Forum
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14 years ago

TimeQuest How to Analyze Slow Ripple Clock

I'm having some trouble analyzing a low speed ripple clock. The original design incorporated a low frequency ripple clock which I believe had timing errors in the hardware. I now want to change the r...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Is there some logic for clk16, or does it come directly from an input port.

When you do report_timing, make sure the -detail is set to full_path. Look at the Data Path tab and make sure the clock paths go all the way back to the input port. If so, it's all being accounted for.

Are you looking in the Fast Corner timing model?

The fitter is quite good at adding routing delays to meet hold timing(assuming Assignments -> Settings -> Fitter -> Optimize Hold is set to All Paths and Optimize Multicorner is checked). How do you know you have a failure?