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Your new problem is by itself a problem hard to understand.
You better use clock on your logic as FPGAs are meant to unless you are after some small combinatorial design in which case you need to tell more about your input/output logic
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https://www.alteraforum.com/forum/attachment.php?attachmentid=8465 Hi kaz, thank you for replying. I mean my design only has the comb part, I want to know the delay of this part. For example when the signal comes to the data_in, how long does it take to get through the comb part then comes out from the data_out.
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