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thanks，I examined the code found that all the logic are combinational logic, which doesn't use clk_1. I think the software‘s optimization omitted clk in compilation.
Now my problem becomes how to find out a pure combinational logic design's delay? In other words, I want to find out how fast the Input changing would not lead the output error.
thanks a lot
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Your new problem is by itself a problem hard to understand.
You better use clock on your logic as FPGAs are meant to unless you are after some small combinatorial design in which case you need to tell more about your input/output logic
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