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Hi there,
I want to use timeQuest to find the max frequency of my design. I never used this tool before, and it's hard for me to get start.
I'm trying to write the sdc file myself, but meet the problem at the very start. I use this command
create_clock -name clk_in -period 40 -waveform {0 20} [get_ports clk_1]
clk_1 is the input in my verilog code, why the timeQuest shows the warning
Warning: Ignored filter: clk could not be matched with a port
Warning: Ignored create_clock: Argument <targets> is an empty collection
Can someone give me a example including the verilog design file and sdc file? Thanks for your help
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The warning says clk(it does not say clk_1) check your sdc statement and make sure the correct file is used
Honored Contributor
