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Hi,
create generated clock for clock output pin which goes to SDRAM chip and constrain output pins to clk_ext
create_generated_clock -name clk_ext -source
set_false_path -to
Create virtual clock and constrain input ports to virtual clock clk_ext_virt
create_clock -name clk_ext_virt -period
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Hi,
Thanks for suggestion ... but "generated clock" is already created by the command
derive_pll_clocks.
There are 2 such clocks (with same frequency) that output from the PLL.
One of them clocks all components in Qsys (including CPU NIOS II), whereas other goes out and clocks
sdram.
The clock that goes to
sdram I pick from the
timequest clock analysis and put it into .SDC using following instruction:
set clk_ext [get_nets u0|pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk]
Then I use it as clock source in
set_input_delay and
set_output_delay.
As I understood (perhaps incorrectly) when the command
derive_pll_clocks is used, it fixes all PLL-generated clocks, isn't it ?
Concerning virtual clock, in all documents that I saw before, virtual clock is used
only if clock is generated
out of FPGA, whereas in my case clock is generated
inside FPGA.
Again, perhaps my perception isn't correct ?
Honored Contributor
