Hi,
Does the design contain any registers? You can see the delay for a combinational logic between registers by reporting the timing between the registers. The Timing Analyzer recognizes and analyzes the following timing paths only.
- Edge paths—connections from ports-to-pins, from pins-to-pins, and from pins-to-ports.
- Clock paths—connections from device ports or internally generated clock pins to the clock pin of a register.
- Data paths—connections from a port or the data output pin of a sequential element to a port or the data input pin of another sequential element.
- Asynchronous paths—connections from a port or asynchronous pins of another sequential element such as an asynchronous reset or asynchronous clear.
Thanks.
Best regards,
KhaiY
New Contributor
