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Altera_Forum
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10 years ago

Timequest difference between 11.1sp1 and 13.1

Have an SDC file with this constraint for some data output signals: set Clock100p0MHz PLL:inst28|……..auto_generated|wire_pll1_clk[3] set_output_delay -add_delay -max 1.0 -clock $Clock100p0MHz...