Timequest default setup relationship through PLLs

Glad to hear you figured it out. The parameters you put into the PLL, like frequency(or multiply/divide), offset, duty cycle are ideal what the PLL looks like and will affect the setup/hold relationships. What then happens physically inside the device beyond that(PLL compensation, clock tree delay, input buffer delay, etc.) are then used as part of the clock path calculation but do not affect the relationships. This is good because the relationship is now calculated independently of what happens during compilation, what device you target, etc. Your slack will change, but not your relationship/requirement.

I know the TQ team has worked to prevent these small relationships from occurring due to rounding, so hopefully 3.333 and 10.0 don't get a 1ps relationship, but I'm not sure if it works across PLLs. (And if the clocks have a funky relationship, such as 2.345ns and 3.141ns, then a 1ps relationship may be correct.)

Finally, for the set_max_delay workaround, that's if all edges are rise-> rise. If you have any rise->fall or fall->rise, or just want to play it safe, I would do the following:

set_max_delay -rise_from clk300 -rise_to clk100 3.333

set_max_delay -fall_from clk300 -fall_to clk100 3.333

set_max_delay -rise_from clk300 -fall_to clk100 1.666

set_max_delay -fall_from clk300 -rise_to clk100 1.666

And if you do mix rise/fall transfers, the hold time changes. It's default is 0ns(when edge aligned, so you have to take care of the phase shift), but for cross-edge:

set_min_delay -rise_from clk300 -rise_to clk100 0.0

set_min_delay -fall_from clk300 -fall_to clk100 0.0

set_min_delay -rise_from clk300 -fall_to clk100 -1.666

set_min_delay -fall_from clk300 -rise_to clk100 -1.666

The one nice thing is you are loosening constraints in all these cases, so if you miss something then the path is overconstrained, but you'll never get the case where it's underconstrained and therefore passes static timing analysis but fails in hardware. (And you can also see that there is more complexity under the hood, whereby something as simple as a 100MHz clock and 300MHz clock has eight assignments to properly constrain it. And if you kept the phase-shift in then the values above would not be as symmetric either.)