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Altera_Forum
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14 years ago

Timequest contraints: pseudo-asynchronous case

Hi all, I am doubtful about how to constraint a few things in a design I have in a Cyclone II FPGA. Basically, the situation is as follows: There is a module A with two processes, Process_...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Thanks a lot!

That was enough (along with the hold constraints) to get what I was looking for and to make sure that my comb delays were small enough. I am still not complying all the paths because I coded things in a way that I don't really have a true register input - comb logic - register output structure, but that's another issue.

Thank you very much for your help!